1. Field of the Invention
The invention relates generally to a dynamic random access memory (DRAM) and a method of fabricating the same. More particularly, the invention relates to a DRAM having at least three layered impurity regions formed between channel holes in an active region of the DRAM and a method of fabricating the same.
A claim of priority is made to Korean Patent Application No. 10-2004-0072354 filed Sep. 9, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Discussion of the Related Art
A dynamic random access memory (DRAM) typically comprises an array of transistors connected to a corresponding set of bitlines and wordlines. Each transistor generally comprises a source and a drain formed in a semiconductor substrate and a gate formed on the semiconductor substrate so as to overlap the source and the drain. The transistor typically further comprises a channel region formed in the semiconductor substrate between the source and drain. The channel region functions as a route for transferring electrical charges between the source and the drain.
As the size of a DRAM decreases, the length of each channel region within the DRAM typically undergoes a corresponding decrease. Due to a phenomenon called the “short channel effect”, the decrease in the channel length may result in a corresponding decrease in the threshold voltage of the transistor.
In an effort to overcome the short channel effect, a transistor having a trench-shaped channel hole formed in a semiconductor substrate has been developed. The trench-shaped channel hole is connected to a word line and functions as a channel region for the DRAM. The channel region transfers charges between source and drain regions along the semiconductor substrate defining the channel hole. The channel hole effectively increases the length of the channel because the distance around the channel hole is longer than the distance across the channel hole.
Unfortunately, transistors using a channel hole to increase the effective length of the channel often experience another phenomenon known as “punch-through”. Punch-through occurs where the drain depletion region and the source depletion region of a transistor overlap, essentially creating a single depletion region. Punch-through typically causes current to rapidly increase as the drain-source voltage is increased.
Punch-through typically occurs where the diameter of the channel hole is so small that impurity ions in the source and drain regions pass directly through the channel hole, thereby increasing a possibility of overlapping each other. In addition, reducing the channel length of a transistor in a DRAM also increases a possibility that impurity ions in the source and drain regions facing each other about the channel portion hole contact along the channel region.
U.S. Pat. No. 6,570,233 (the '233 patent) discloses a method of fabricating an integrated circuit. According to the method, source and drain regions are formed in a semiconductor substrate and a gate is formed on the semiconductor substrate so as to overlap the source and drain regions. An insulating layer is then formed to cover the transistor and a contact hole is formed in the insulating layer. A thin first layer is formed on one of the source and drain regions to cover the contact hole. The first layer is formed using a conductive material having a first concentration of dopants. Next, a second layer is formed to cover the first layer. The second layer is formed using a conductive material having a second concentration of dopants which is lower than the first concentration of dopants. Together, the first and second layers form a contact plug.
After the first layer is formed, impurity ions having a first energy level are injected into at least one of the source and drain regions. Then, impurity ions having a second energy level higher than the first energy level are injected into the at least one of the source and drain regions via the first layer. By doing so, a contact resistance between the contact plug and the semiconductor substrate are reduced.
Although the method uses complicated processes in order to reduce the contact resistance between the contact plug and the semiconductor substrate, a problem arises where ions from the ion implantation processes and dopants in the contact plug are excessively diffused, thereby causing a short channel effect.
Because of at least these problems, improved DRAM manufacturing techniques are needed.